High resolution, high speed analog-to-digital converters (ADCs) can require buffers to isolate a high impedance track-and-hold (TAH) stage from one or more sample-and-hold (SAH) stages preceding the ADC. In some cases, buffers can be used to isolate successive SAH stages. Such buffer implementations can be a key component in enabling and advancing high speed communication (e.g., 100 Gigabit Ethernet) networks and systems. For example, a 28 Gbps serial link communication receiver might require multiple successive approximation register (SAR) ADCs, each with one or more buffers exhibiting at least the following characteristics: wide bandwidth, very fast large signal settling and slewing (e.g., low output impedance), high linearity over the full analog input signal, low noise, high power supply rejection, and high input impedance over the wide bandwidth (e.g., near or in excess of the Nyquist rate). Such receivers might also demand the buffer exhibit low power consumption, which introduces further demands that the buffer gain to be near unity. For example, a unity gain buffer might enable the buffer and the ADC to be powered by a common low supply voltage (e.g., 1V), providing both low power consumption by the buffer, and full use of the available ADC dynamic range.
Legacy buffer designs can exhibit some of the aforementioned characteristics, but fall short of achieving all of the aforementioned required buffer performance characteristics. For example, a legacy source-follower buffer can have high bandwidth, but only moderate linearity and overall signal settling. The source-follower buffer can also exhibit asymmetric positive and negative slewing. Other legacy buffer designs might address one or more performance issues (e.g., asymmetric slewing or linearity), but do not achieve all the aforementioned buffer characteristics required for advancing low power, high speed communication system implementations. Further, the legacy buffer designs exhibit DC level shifts and gains less than unity (e.g., 0.7-0.8), further decreasing linearity and increasing power consumption. For example, to provide a signal to an ADC operating at 1V such that the full ADC dynamic range is utilized, a legacy buffer design with a gain of 0.7 might require a supply voltage of 1.4V, increasing the power consumption as compared to a buffer with unity gain and operating at a lower supply voltage.
Techniques are needed to address the problem of implementing a low power buffer that exhibits unity gain across a wide bandwidth. None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed techniques for a low power buffer with gain boost. Therefore, there is a need for improvements.